//************************************************
//  Filename      : iir_top.v                             
//  Author        : Kingstacker                  
//  Company       : School                       
//  Email         : kingstacker_work@163.com     
//  Device        : Altera cyclone4 ep4ce6f17c8  
//  Description   :                              
//************************************************
module  iir_top #(parameter WIDTH = 16)(
    //input;
    input    wire    sys_clk,
    input    wire    rst_n,
    //output;
    output   wire  [WIDTH-1:0]  dout 
);
wire clk;
wire [WIDTH-1:0] q;
pll_1  pll_1_1(
    .inclk0             (sys_clk),
    .c0                 (clk)
);

iir  iir_1(
    .clk                (clk),
    .rst_n              (rst_n),
    .din                (q),
    .dout               (dout)
);
signal  signal_1(
    .clk                (clk),
    .rst_n              (rst_n),
    .q                  (q)
);

endmodule